(Research Triangle Park, N.C.) ViASIC Inc., a leading electronic design automation company that offers IP and services for reconfigurable semiconductor fabrics, today announced the results of the recently held Workshop on Radiation Hardened Structured ASIC design instantiation. The Air Force Research Laboratory, Micro-RDC and ViASIC sponsored this four-day workshop last month in Albuquerque, N.M. to allow attendees to begin with a functionally verified RTL circuit description and work through the design flow to produce a GDS-II file ready for fabrication.

Participants at the workshop either brought their own RTL design or used a tutorial design provided at the workshop. Course materials, workstations, and field application engineers were provided to walk designs through the entire process. In addition to Micro-RDC and ViASIC, additional support from Incentia Design Systems and several other EDA suppliers helped attending designers complete their flows and allowed ViASIC’s ViaPath to be used in conjunction with other tools.

Participants from eight companies took their designs through all stages of the development flow — from freshly synthesized RTL through memory and hard macro generation, place and route, timing closure, and test to final GDS-II generation, design rule checking (DRC) and layout-versus-schematic. Four customer-supplied designs were taped out, ranging in size and complexity. In February, 2010 each participant will receive 40 free, rad-hard chips as a result of attending the workshop.

“Attendees were impressed with ViaPath’s ability to reconfigure with only one via layer, fit into a conventional ASIC flow, yet maintain much of the simplicity expected in an FPGA flow. Several of the attendees with FPGA experience had never worked with a custom ASIC, but were still able to complete the process on their own designs to tape-out during the workshop,” said Mark Goode, president and chief executive officer of ViASIC. “Not only did they get free prototypes as a result of attending, they could also see how this approach cuts design time, cost and risk. In fact, we have had so many inquiries from these attendees for additional workshops, and from commercial companies for non-rad hard chips, that we are looking into a new series of workshops for 2010.”  

ViASIC’s ViaPath™ place and route software performs optimization, placement and routing for standard metal (one-mask or two-mask) programmable designs. The principles used in ViaPath are equally effective for structured ASICs and synchronous or asynchronous RAM-based FPGAs, resulting in a correct-by-construction finished IC design that meets all design closure requirements. For additional information, see http://viasic.com/products/viapath/

ViASIC Inc. is the leading supplier of electronic design automation (EDA) tools, IP and services for reconfigurable semiconductor fabrics, both with and without SRAM. Reconfiguring far fewer metal layers than alternative approaches, ViASIC slashes design cost, time and risk. It enables ASSP providers, product designers, test chip designers, and other customers to reduce mask costs by up to 95% versus a standard ASIC design approach. The company also speeds time to market by allowing manufacturing to begin before the design is fully completed and by allowing silicon debug much earlier in the design flow. Founded in 2000, ViASIC is headquartered in Durham, N.C. For more information about ViASIC and its products and services, visit www.viasic.com